High Speed Communication Circuits and Systems

نویسنده

  • Michael H. Perrott
چکیده

This project will explore issues associated with implementing a GMSK (Gaussian Minimum Shift Keying) transmitter that is intended for use in GSM cell phones. This communication standard encodes information using phase modulation of a constant envelope sine wave signal. By constraining the transmitter output to have constant envelope, a nonlinear power amplifier can be used that broadcasts the signal with high efficiency (usually around 50% efficiency, as compared to about 10% efficiency encountered with linear power amps). A proposed transmitter for this task is shown in Figure 1, which employs a PLL that contains an I/Q modulator in its feedback loop. As you proceed through the project, you will (hopefully) come to understand the value of placing the I/Q modulator in the PLL feedback loop rather than directly using its output as the transmitter output, and develop a good understanding of RF transceivers in general. Figure 2 displays the proposed receiver used to select and demodulate the desired GMSK RF signal, which is implemented using a direct conversion architecture. For simplicity, we will ignore the many difficulties encountered with this structure, such as high sensitivity to DC offsets, antennae impedance variations, and local oscillator feedthrough. The noise source in the figure represents the overall input-referred noise of the receiver (it is not, of course, purposefully added!).

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Symmetrical, Low-Power, and High-Speed 1-Bit Full Adder Cells Using 32nm Carbon Nanotube Field-effect Transistors Technology (TECHNICAL NOTE)

Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other ...

متن کامل

Reducing Hardware Complexity of Wallace Multiplier Using High Order Compressors Based on CNTFET

   Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and red...

متن کامل

Switched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

متن کامل

High Speed Integrated Circuits for High Speed Coherent Optical Communications

High Speed Integrated Circuits for High Speed Coherent Optical Communications by Hyun-chul Park With the development of (sub) THz transistor technologies, high speed integrated circuits up to sub-THz frequencies are now feasible. These high speed and wide bandwidth ICs can improve the performance of optical components, coherent optical fiber communication, and imaging systems. In current optica...

متن کامل

High-Speed Ternary Half adder based on GNRFET

Superior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half a...

متن کامل

A High-Speed Dual-Bit Parallel Adder based on Carbon Nanotube ‎FET technology for use in arithmetic units

In this paper, a Dual-Bit Parallel Adder (DBPA) based on minority function using Carbon-Nanotube Field-Effect Transistor (CNFET) is proposed. The possibility of having several threshold voltage (Vt) levels by CNFETs leading to wide use of them in designing of digital circuits. The main goal of designing proposed DBPA is to reduce critical path delay in adder circuits. The proposed design positi...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2003